1. Field of the Invention
The present invention relates to a method for designing a logic circuit and, more particularly, to a method for designing a high-performance logic circuit in a short period of time.
2. Description of Related Art
In the current design of a logic circuit, a method in which a logic function is described at a register transfer level or an operation level in a logic description language termed an HDL (Hardware Description Language) and the logic described at the register transfer level or the operation level is converted to gate level logic by using a CAD tool for logic synthesis is used most prevalently. The register transfer level explicitly describes required registers and arithmetic units in conjunction with data paths and control paths for providing connection between the registers and the arithmetic units. At present, the register transfer level is a description level used most frequently for a logic circuit in the design thereof. The operation level is a description level higher in the degree of abstractness than the register transfer level. The operation level describes a control structure, similarly to a software language, and does not explicitly describe registers and arithmetic units as circuit elements. The operation level is also termed an algorithm level or a behavior level.
In general, circuit components termed cells have primitive logic functions such as AND logic and OR logic and are designed preliminarily. A CAD tool for logic synthesis stores the respective characteristics of the individual cells including logic function, layout size, delay, and power consumption in the library thereof. By converting a logic function described at the register transfer level or the operation level to a logic function such as AND, OR, or NOT and allocating the cells in the library to the logic function, a logic circuit described in the connectional relation of the cells, i.e., a gate level logic circuit can be obtained from the logic function described at the register transfer level or the operation level. The gate level logic circuit is passed to a layout step as the subsequent design process.
In the foregoing logic synthesis process, synthesis constrains are placed on the allocation of the cells in the library. The first synthesis constraint is the target values of the design specifications of a logic circuit including circuit area, operating speed, and power consumption. The structure of the logic circuit should be determined to satisfy the specifications. The second synthesis constraint is conditions external to the logic circuit, which include the load capacitance of a cell for driving the input port of a logic circuit for which logic synthesis is performed, the load capacitances of a wire and a cell connected to the output port of the logic circuit, the time at which a signal reaches the input port, and a time required by the signal from the output port to reach an external flip flop. The third synthesis constraint is the wiring load of the logic circuit that has been laid out. For example, a wiring load assumed based on a virtual wiring load model is given as a load capacitance on a per fan-out basis.
Thus, the logic synthesis process is provided with the logic circuit described in an HDL, the synthesis constraints, and the cell library, performs the steps of optimizing a logic structure and allocating cells, and outputs the gate level logic circuit of the logic circuit. The primary object of the design of a logic circuit at the register transfer level or the operation level is normally the implementation of a target logic function so that, in most cases, sufficient consideration is not given to the physical characteristics of the logic circuit when it is implemented as an actual semiconductor device such as circuit area, operating speed, and power consumption. Accordingly, the correction of an HDL description, logic synthesis, and the evaluation of the circuit area, operating speed, power consumption, and the like of a gate level logic circuit obtained as a result of logic synthesis are repeated several times so that the target specifications are approached.
Even when the design starts from the same HDL description, the gate level logic circuit and the characteristic thereof differ if different CAD tools are used for logic synthesis.
With the remarkable progress of digital information equipment represented by a personal computer, the performance required of a semiconductor chip forming the heart of the digital information equipment has been improved rapidly year after year. The operation frequency is exceeding 1 GHz, while lower power consumption is stringently required of a semiconductor chip used in a battery-powered mobile information device, such as a mobile phone, for a longer battery life. The design of a logic circuit should be performed to satisfy these stringent requirements. This causes the problem that, even if a design period is reduced by distributing design resources and increasing the degree of abstractness of a logic description level, the design period of the logic synthesis process for achieving desired performance is increased and the total design period of a whole semiconductor chip cannot sufficiently be reduced. The following is a typical example. To provide a semiconductor chip with a target operation frequency, it is necessary for delay in each of signal paths in a logic circuit to fall within a target cycle so that, even if only one signal path falling outside the target cycle exists, the target frequency is not achievable. Accordingly, the delay design of a logic circuit requires a longest design period in the logic synthesis process.
To reduce such a design operation, numerous CAD tools for logic synthesis equipped with advanced function and performance have been on sale. Since the process performed by CAD for logic synthesis is used to solve a so-called combinational optimization problem by searching for an optimal solution closer to a design objective among numerous candidate solutions, it is impossible to select the best one by evaluating all solutions in a practical time. Each of the CAD tools for logic synthesis has been developed by improving an algorithm and thereby enhancing the ability to search for an optimal solution. This frequently causes the situation in which a CAD tool A generates a better circuit with design data A, while a CAD tool B allows the generation of a circuit higher in performance with design data B. Therefore, it is costly and unpractical for one design site to purchase a variety of CAD tools for synthesis.
In recent years, a new form of business service termed an application service provider has been offered in various software fields. This form of business service allows each company to access the server of a provider who provides software by using the Internet, use software through a network only when necessary, and pay a fee charged for the use by saving the conventional practice to purchase a required number of software items and operate and manage them on its own.
If this form of business service is used for the design of a logic circuit, however, design data which requires security protection is transferred by input/output operations through the network so that a problem associated with the security protection of design data is encountered. Another problem is encountered that large-sized input/output data increases cost and time for communication and therefore this form of business service is not compatible with promptly or repeatedly performed design. Still another problem is encountered that, if circuit characteristics obtained by using software at the cost of a service charge are unsatisfactory, the service charge is wasted for nothing. If the correction of an HDL description, logic synthesis, and the evaluation of the area, operating speed, power consumption, and the like of a gate level logic circuit obtained as a result of logic synthesis are repeated such that target specifications are approached, in particular, the use of software is charged frequently in the process of trial and error. This causes the problem that a tremendous service fee is charged by the time the target specifications are obtained.